1. Field
Exemplary embodiments of the present invention relate to an impedance control circuit generating an impedance control code for controlling an impedance value.
2. Description of the Related Art
Various types of semiconductor devices are integrated as integrated circuit chips such as CPUs, memories, gate arrays, and the like, in various electrical products such as a personal computer, a server, a workstation, and the like. In most cases, a semiconductor device includes a receiver circuit for receiving various signals transmitted from the outside through an input pad and an output circuit for transmitting signals from the semiconductor device to the outside through an output pad.
Meanwhile, as an operation speed of electrical products is increased, a swing width of signals that are transmitted between the semiconductor devices is reduced. The reason is to minimize a delay time consumed to transfer the signals. However, as the swing width of the signals is reduced, an influence on the signals by external noises is increased and the reflection of the signals increase at interface ends of the semiconductor devices due to impedance mismatching (referred to as mismatch). The impedance mismatching occurs due to a fluctuation in external noises or power supply voltages, a change in operation temperature, a change in manufacturing processes, or the like. When the impedance mismatching occurs, it is difficult to transmit data at a high speed and distorted data may be output from a data output end of the semiconductor device. Therefore, when the other semiconductor device receives the distorted output data as an input data at an input end, a setup/hold fail, a misjudgment of an input level, or the like, may be caused in the input data.
In particular, in order to increase the operation speed of the memory device, impedance matching circuits called on die termination are adopted in the vicinity of pads within an integrated circuit chip. In the on die termination scheme, source termination is performed by an output circuit of a transmitting semiconductor device and parallel termination is performed by a termination circuit connected, in parallel, to a receiver circuit of a receiving semiconductor device that is connected to the input pad thereof.
ZQ calibration means a process of generating an impedance code changing in response to PVT (process, voltage, temperature) conditions. A termination impedance value is controlled using the impedance code generated as the ZQ calibration results. Generally, the pad connected to the external resistor that is a reference of calibration is referred to as a ZQ pad. For this reason, the term ZQ calibration is mainly used.
Hereinafter, an impedance control circuit 10 performing the calibration will be described.
FIG. 1A is a diagram illustrating an impedance control circuit 10 and an impedance control circuit control unit 15 in accordance with the conventional art.
The impedance control circuit control unit 15 controls an operation of the impedance control circuit 10, which will be described with reference to FIG. 1B.
The impedance control circuit 10 in accordance with the conventional art illustrated in FIG. 1A may include a pull-up impedance unit 40, a dummy impedance unit 60, a pull-down impedance unit 90, pull-up and pull-down comparators 20 and 70, and pull-up and pull-down counter units 30 and 80.
When the calibration operation starts, a calibration enable signal CAL_EN is enabled. The pull-up comparator 20 responds to the enabled calibration enable signal CAL_EN to compare reference voltage VREF (for example, VDD/2) with voltage of a first node (ZQ node), which is generated by voltage division of an external resistor RZQ (for example, 240Ω) connected to the ZQ pad and the pull-up impedance unit 40, and generates a first up/down signal UP/DN1 depending on comparison results.
When the calibration enable signal CAL_EN is enabled, the pull-up counter unit 30 receives the first up/down signal UP/DN1 to generate a pull-up impedance control code PCODE<N:0>. The pull-up impedance control code PCODE<N:0> turns on/off parallel resistors (the impedance value, e.g., the resistance value, of each of the parallel transistors may be designed to correspond to a binary weight) to control the impedance value of the pull-up impedance unit 40. The controlled impedance value of the pull-up impedance unit 40 again affects the voltage of the first node (ZQ node) and the above-mentioned operation is repeated. Consequently, the calibration operation is repeated (pull-up calibration) until the whole impedance value of the pull-up impedance unit 40 is equal to the impedance value of the external resistor RZQ.
The pull-up impedance control code PCODE<N:0> generated by the aforementioned pull-up calibration operation is input to the dummy impedance unit 60 to determine the whole impedance value of the dummy impedance unit 60.
Thereafter the pull-down calibration operation starts to be similar to the case of the pull-up calibration. The calibration is performed (pull-down calibration) so that voltage V2 of a second node is equal to the reference voltage VREF, that is, the whole impedance value of the pull-down impedance unit 90 is equal to the whole impedance value of the dummy impedance unit 60 by using the pull-down comparator 70 performing the comparison operation to generate a second up/down signal (UP/DN2) when the calibration enable signal CAL_EN is enabled and the pull-down counter unit 80 receiving the second up/down signal UP/DN2 to generate a pull down impedance control code NCODE<N:0> when the calibration enable signal CAL_EN is enabled.
FIG. 1B is a diagram illustrating the impedance control circuit control unit 15 in accordance with the conventional art illustrated in FIG. 1A.
The impedance control circuit control unit 15 may include a clock counter unit 15A and a control logic unit 15B. The clock counter unit 15A counts a clock CLK to output a counting code CNT<Y:0>. More specifically, the clock counter unit 15A increases its own value of the counting code CNT<Y:0> whenever the clock CLK is enabled and input from the instant that a calibration command ZQC is enabled and input. The control logic unit 15B operates the impedance control circuit 10 until the value of the counting code CNT<Y:0> reaches a given value depending on a type of calibration operation. For example, the control logic unit 15B operates the impedance control circuit 10 by enabling the calibration enable signal CAL_EN until the counting code CNT<Y:0> is 64 in the case of a short calibration mode. In addition the control logic unit 15B operates the impedance control circuit 10 by enabling the calibration enable signal CAL_EN until the counting code CNT<Y:0> is 512 (or 256) in the case of a long calibration mode.
FIG. 2 is a diagram illustrating a termination circuit in accordance with the conventional art that includes a plurality of pull-up termination units 220A, 220B, . . . , 220C and a plurality of pull-down termination units 270A, 270B, . . . , 270C. The termination circuit means a circuit that receives the impedance control codes PCODE<N:0> and NCODE<N:0> generated in the impedance control circuit 10 illustrated in FIG. 1 to terminate an interface pad. i.e., to determine an impedance value thereof. The impedance value of each pull-up termination units 220A, 220B, . . . , 220C may equal or different to or from the impedance value of each of the pull-down termination units 270A, 270B, . . . , 270C. (Hereinafter, the impedance values of each of all of the termination units 220A, 220B, . . . , 220C, 270A, 270B, . . . , 270C) are described to be 240Ω).
Each of the plurality of pull-up termination units 220A, 220B, . . . , 220C is designed to be similar to the pull-up impedance unit 40. Further, since the impedance values are determined by the same pull-up impedance control code PCODE<N:0>, each of the pull-up termination units 220A, 220B, . . . , 220C and the pull-up impedance unit 40 have the same or similar tendency.
The pull-up driver controller 210 controls each of the pull-up termination units 220A, 220B, . . . , 220C in response to the pull-up impedance control code PCODE<N:0> and the pull-up enable signal PU_EN. The pull-up enable signal PU_EN is a signal that turns on/off each of the pull-up termination units 220A, 220B, . . . , 220C. For example, when the pull-up enable signal PU_EN is enabled, the resistors within the first pull-up termination unit 220A are turned on/off in response to the pull-up impedance control code PCODE<N:0>. Meanwhile, when the pull-up enable signal PU_EN is disabled, the first pull-up termination unit 220A are not operated regardless of the pull-up impedance control code PCODE<N:0>. That is, all of the resistors within the first pull-up termination unit 220A are turned off.
Meanwhile, a pull-up driver controller 210 enables at least one of the plurality of pull-up termination units 220A, 220B, . . . , 220C in response to a mode register set signal MRS<2:0>. For example, when the targeted impedance values of the plurality of pull-up termination units 220A, 220B, . . . , 220C are set to be 120Ω, the pull-up driver controller 210 performs a control to enable only two of the plurality of pull-up termination units 220A, 220B, . . . , 220C in response to the mode register set signal MRS<2:0> and disable the remaining pull-up termination units. When two resistors of 240Ω are connected in parallel, resistance is 120Ω. The resistors within the enabled pull-up termination unit are turned on/off in response to the pull-up impedance control code PCODE<N:0>. All of the resistors within the disabled pull-up termination unit are turned off.
Each of the plurality of pull-down termination units 270A, 270B, . . . , 270C is designed to be similar to the pull-down impedance unit 90. Further, since the impedance values are determined by the same pull-down impedance control code NCODE<N:0>, each of the pull-down termination units 270A, 270B, . . . , 270C and the pull-down impedance unit 90 have the same or similar tendency.
The pull-down driver controller 260 controls each of the pull-down termination units 270A, 270B, . . . , 270C in response to the pull-down impedance control code NCODE<N:0> and the pull-down enable signal PD_EN. The pull-down enable signal PD_EN is a signal that turns on/off each of the pull-down termination units 270A, 270B, . . . , 270C. For example, when the pull-down enable signal PD_EN is enabled, the resistors within the first pull-down termination unit 270A are turned on/off in response to the pull-down impedance control code NCODE<N:0>. When the pull-down enable signal PD_EN is disabled, the first pull-down termination unit 270A are not operated regardless of the pull-down impedance control code NCODE<N:0>. That is, all of the resistors within the first pull-down termination unit 270A are turned off.
Meanwhile, the pull-down driver controller 260 enables at least one of the plurality of pull-down termination units 270A, 270B, . . . , 270C in response to the mode register set signal MRS<2:0>. For example, when the targeted impedance values of the plurality of pull-down termination units 270A, 270B, . . . , 270C are set to be 60Ω, the pull-down driver controller 260 performs a control to enable only four of the plurality of pull-down termination units 270A, 270B, . . . , 270C in response to the mode register set signal MRS<2:0> and disable the remaining pull-down termination units. When four resistors of 240Ω are connected in parallel, resistance is 60Ω. The resistors within the enabled pull-down termination unit are turned on/off in response to the pull-down impedance control code NCODE<N:0>. All of the resistors within the disabled pull-down termination unit are turned off.
When using the plurality of termination units, various impedances may be set, but an error occurs between the targeted impedance value and the actual impedance value due to parasitic resistance occurring in a layout. Generally, when the termination operation is performed, the enabled pull-up termination unit and the enabled pull-down termination unit are set to have the same impedance value. However, as the number of enabled pull-up termination units and the number of enabled pull-down termination units are increased, the error of the impedance value may be increased due to the parasitic resistance. The error is called RTT MISMATCH, which may be obtained by Equation (2VM/VDD−1)*100 and has a unit of %. Here, VM means the voltage of the interface node (meaning a node to which the interface pad is connected) of the termination circuit (FIG. 2). The mismatch degree of the impedance value of the enabled termination unit may be determined by using the value of the VM depending on a voltage division rule.
FIGS. 3A and 3B are diagrams illustrating RTT MISMATCH depending on the targeted impedance value in the termination circuit in accordance with the conventional art.
As the number of termination units connected in parallel is increased, the impedance mismatch is also increased due to the parasitic resistance occurring in the layout. FIGS. 3A and 3B illustrate shapes in which the RTT MISMATCH is increased based on the targeted impedance value 120Ω of the termination unit.
FIG. 3A is a diagram illustrating a case in which the RTT MISMATCH has a positive value.
A ratio of the impedance value of the enabled pull-down termination unit to the impedance value of the enabled pull-up termination unit is equal to a ratio of VM to VDD-VM by the voltage division rule. As illustrated in FIG. 3A, the case in which the I′M MISMATCH has a positive value means that the impedance value of the enabled pull-up termination unit is smaller than that of the enabled pull-down termination unit by the aforementioned Equation in the description of FIG. 2.
FIG. 3B is a diagram illustrating a case in which the RTT MISMATCH has a negative value.
A ratio of the impedance value of the enabled pull-down termination unit to the impedance value of the enabled pull-up termination unit is equal to a ratio of VM to VDD-VM by the voltage division rule. As illustrated in FIG. 3B, the case in which the RTT MISMATCH has a negative value means that the impedance value of the enabled pull-up termination unit is larger than that of the enabled pull-down termination unit by the aforementioned Equation in the description of FIG. 2.
The RTT MISMATCH values may be increased to affect the input/output of data under the layout condition.